Published: 16 Mar 2023 · Last updated: 16 Mar 2023
The higher cost of SiC compared to silicon, and a limitation in substrate supply have been significant contributing factors inhibiting widespread SiC adoption for power devices. Device manufacturers are scaling production to bring down cost per die in addition to moving from 150 mm to 200 mm wafer size, and maintaining the device yield levels at the larger 200 mm wafer size has proved challenging. Plasma Polish, launched by Oxford Instruments in 2022 at ICSCRM, Davos, is a scalable solution designed to increase yield and can therefore alleviate some of the technical challenges limiting SiC adoption. This innovative dry plasma etch process is a validated and cost-effective alternative approach to chemical mechanical polish (CMP), for preparing SiC substrates for epi. Plasma Polish is uniquely able to target and remove subsurface damage that limits yield, and leave the remaining SiC surface in ideal condition for epi deposition and device fabrication. The benefits of Plasma Polish have been externally validated and subsequently demonstrated on sample material from multiple EMEA, USA and Asian SiC device and substrate manufacturers. Oxford Instruments are accelerating final-stage qualification programs with key industry partners and ramping Plasma Polish system production to support anticipated scaling demands.
The growing importance of silicon carbide (4H-SiC) components in E-mobility, as well as in other sectors such as sustainable energy, is prompting the wide bandgap supply chain to develop existing and new technologies and processes, customized to the materials' characteristics and performance. Their aim is to meet the performance, reliability and volume demands of consumers in these high-growth markets. Driven by greater efficiency, higher power, faster switching and smaller form factors compared to silicon, the SiC industry is growing rapidly in response to increasing performance and system-level cost reductions. Increasingly, when designing power systems operating above 400 V, SiC device-based modules are a very attractive option. These factors are taken into consideration with a SiC device market growth projection of 34% CAGR, with the market size expected to increase from ~$1B in 2021 to ~$6B in 2027 [1].
The transition from 150 mm to 200 mm SiC that the industry is currently undergoing, will play a significant role in generating the projected growth – 200 mm yields more devices. Wafer and device yield is expected to dip [3] (as it did from 100 mm to 150 mm before recovering), with analysts predicting the lag to be a couple of years for 200 mm to really start paying off. This means that innovative cost-effective and quality enhancing SiC-specific solutions, such as Plasma Polish, are of paramount importance to initially reduce costs and increase yield at 150 mm and 200 mm later, thereby supporting the desired industry growth.
"The introduction of 200 mm substrates is expected to bring down the overall device cost by 20–35 percent relative to production on a 150 mm platform." — CS Magazine 2021
"…a move to 200 mm substrates is unlikely to radically drop the SiC cost immediately. In fact, in every scenario we run, there is likely to be a premium to pay for using 200 mm substrates initially, until the wafer yield and die yield begin to return to 150 mm levels." — Peter Gammon PGC Consultancy
For yield increases to occur at any wafer size, SiC processing techniques that specifically target and remove subsurface damage from previous wafering steps are vitally important. Developed for processing much softer silicon, CMP is currently the process of record for the final wafer polishing step before epitaxy and device fabrication. Although CMP has a positive effect on improving surface quality, variation wafer-to-wafer with CMP can be difficult to control because CMP primarily targets the surface, making it much less efficient in removing subsurface damage that can remain after previous grinding steps. Furthermore, the chemical mechanical nature of the process means it is hard to predict if we truly removed the desired subsurface damage, which can negatively impact the epi quality due to the formation of defects that cause lower device yield.
Plasma Polish is a specially designed, clean and cost-effective SiC polishing technique, that targets defective and weakly bonded material in the surface and sub-surface. Due to a proprietary balance of chemistry and powers delivered to the wafer at low pressure, the non-contact plasma reaction uses ions and radicals to physically knock off and chemically attach to damaged SiC surface and subsurface. The material that remains is damage-free, high-quality and prevents the subsurface issues that can be present from previous grinding steps from transferring to the epi. If this subsurface damage is not fully removed, then it can impact the subsequent SiC epi-deposition by means of defect propagation from the substrate and the formation of new defects that are detrimental for diodes and MOSFET devices. [4]
Plasma Polish is performed on Oxford Instruments Plasma ICP/RIE etcher on the Si face of >150 mm, 4H-SiC, 350 µm thick, 4° offcut substrates that have had fine grind done and are ready for the polishing step. During the process, 2.9 µm thickness was removed, with a marginal change in bow post processing. The surface roughness was measured by Atomic Force Microscopy (AFM), before and after the process, with results shown in Fig 1a – b respectively. The data shows that Plasma Polish improves surface smoothness by 50% Ra (from 1.5 nm to 0.7 nm) by reducing scratch density and depth.
To compare Plasma Polish and CMP surface quality, data on the properties of the epi-layers and devices such as JSB and MOSFETs grown on substrates from the same boule and treated by Plasma Polish and CMP respectively is presented. A nominal 12.7 µm thick SiC layer with N2 doping of 8e15 cm⁻³ was deposited by MOCVD on both kinds of substrates. Thickness and doping density of the epi-layers were confirmed across the wafers by FTIR and C-V respectively, with uniformity below 5%. Afterwards, density of dislocations by KOH etch, optical/PL inspections and epi-surface roughness by AFM were measured, and Candela (optical/PL) inspections and AFM were taken to categorize the surface and defects before and after epi.
Fig. 1 — AFM images: a. unpolished substrate (Ra = 1.5 nm); b. after Plasma Polish (Ra = 0.70 nm); c. SiC epi-layer on Plasma Polish wafer (Ra = 0.14 nm); d. SiC epi-layer on a CMP wafer (Ra = 0.12 nm).
AFM on epi-layers grown on Plasma Polish and CMP substrates show similar roughness, 0.12 nm and 0.14 nm, respectively (Fig 1c and d). Defect mapping by Candela (Fig 2) shows a higher Total Usable Area (TUA – defined here as the ratio between 2×2 mm squares containing a maximum of 1 defect by the total number of such squares across the wafer) for the epi-layer grown on Plasma Polish than the standard CMP process. It also shows a lower count of "killer" defects, such as scratches, micropits, triangles and epi-defects, on wafers processed with Plasma Polish.
Fig. 2 — Optical/PL mapping of epi-layers grown on a) CMP and b) Plasma Polish substrates, showing defect types detected and TUA calculated for each mapping.
To validate the quality of Plasma Polish through to device, merged pin diodes (MPD) were fabricated by Clas-SiC (Clas-sic Wafer Fab Ltd, Scotland UK) on the epi-layers deposited on both CMP and Plasma Polish substrates and their electrical performance was compared. Electrical measurements were performed both in the on-state up to 5V and off-state voltages at 600V and 1200V. Breakdown voltage (Vb) and leakage current (Ir) were measured for every die (c. 3000) and the percentage of dies passed is shown in Table 1.
| MPD parameter | CMP | PPDE |
| Vb at 500 µA | 89 | 93 |
| Ir at 600 V | 91 | 97 |
| Ir at 1200 V | 95 | 97 |
Table 1. Dies (%) passed for CMP (column 2) and Plasma Polish (column 3) about Vb (row 1), Ir (row 2 and 3).
The roughness (Ra) reduction assessment was comparable for Plasma Polish and CMP, and in line with industry requirements, in that roughness for the incoming material was reduced by around 50% in each case. Damage elimination performance was better for Plasma Polish, resulting in a higher total usable area of 94% compared to 84% for CMP – this damage-removal effect can typically be observed on Plasma Polished wafers where the etch rate in damaged and defective areas is higher, producing a characteristic damage-free wavey SiC surface morphology. Finally, the device data results for dies grown on Plasma Polish substrates compared to those grown on CMP substrates, again exhibit a higher percentage of dies passed for Plasma Polish. In summary, Plasma Polish is a high-quality, high yielding process that has been validated through to device fabrication with excellent performance. The characteristics of the process are such that targeting damage removal at the subsurface level is a key benefit of the technology, which sets Plasma Polish apart from the current process of record.
The technique has been developed specifically for SiC and uniquely brings the ability to target and remove subsurface damage, with the result being high yielding and high performing devices. With intensive qualification projects in the final stages with several leading manufacturers, it's been found that Plasma Polish can be applied, with great effect, to improve substrate surface and subsurface for multiple production processes, where SiC crystal quality is a critical yield limiting factor. The process is currently being tested with commercial partners at several points in the SiC device fabrication supply chain, such as boule growth, pre and post-epi, and, in between epi layers to meet the requirements needed for higher voltage devices.
200 mm compatible etch platform with industry standard automated handler.
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